数字电路实验课程小结

课程小结

这学期通过九周的数字电路的实验,既对门电路、译码器、触发器、计数器等理论知识有了更深的理解,又锻炼了自己实际的操作能力。在已有的课本知识基础上进行实验设计,使同学们在传统实验基础上的创新意识得到体现,同时又巩固了对数字电路的掌握,激发了我们的学习数字电路的兴趣。

首先在做实验之前要要有充分的准备,弄懂实验原理,实验总是与课本知识相关的,就必须回顾课本的知识,掌握相关的知识点。在实验过程中,我们应该尽量减少操作的盲目性提高实验效率的保证,在弄懂了实验原理的基础上,才能保证自己的正确性。

在写预习报告时,会通过仿真,提出问题并试着通过网络找资料自学有关知识以及与他人交流来解决问题。培养了自己发现问题和解决问题的能力,留给学生充分的学习思维时间,增强了学习的主动性,为在课堂上的进一步理解应用打下基础。

同时将两个人组成一小组,再将几小组组成一个大组的形式很好,增强了大家的互动性。无论是在课后还是课上,大家都可以不断交流,互相发现问题,解决问题,在遇到不懂的地方共同努力,齐心协力,共同进步。

数字电子技术实验的开放体现了学生的主体意识,同学们在实验中表现出了积极的主动性。在实验中应思考如何去掌握和运用物理方法,如给定了实验原理和一些条件要求(如相关的芯片),设计实验方案、实验步骤,画出实验电路图,然后进行操作,得出结果。

数字电子技术是一门理论性和实践性都很强的专业基础课,也是一门综合性的技术基础学科,许多理论和方法只有通过实际验证才能加深理解并真正掌握。在老师的启发引导下,通过创新解决问题,获取知识,掌握物理实验思想和实验方法的实质,从而培养创新能力。学习数字电路实验这门课程,要掌握电路设计的基本知识和方法,通过实验培养在实践中研究问题、分析问题和解决问题的能力,为将来从事技术工作和科学研究奠定扎实的基础。

 

第二篇:VHDL数字电路课程实验报告

VHDL数字电路课程实验报告

实验一  8分频器

一、实验要求:分别用信号量和变量实现八分频器

二、实验过程:

1、代码:

8分频器vhd

library ieee;

use ieee.std_logic_1164.all;

entity freq_divider is

port(clk: in std_logic;

     out1, out2: buffer bit);

end freq_divider;

architecture example of freq_divider is

signal count1: integer range 0 to 7;

begin

process(clk)

variable count2: integer range 0 to 7;

begin

if(clk'event and clk='1') then

count1<=count1+1;

count2:=count2+1;

if(count1=3) then

out1<=not out1;

count1<=0;

end if;

if(count2=4) then

out2<=not out2;

count2:=0;

end if;

end if;

end process;

end example;

八分频器tb

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY fd_tb is

END fd_tb;

architecture behavior of fd_tb is

component freq_divider

port(clk:IN STD_LOGIC;

        out1, out2: buffer bit);

end component;

signal clk:std_logic;

signal out1,out2:bit;

begin

u1: freq_divider port map(clk,out1,out2);

process

begin

clk<='0';

wait for 50 ns;

loop

clk<=not clk;

wait for 25 ns;

end loop;

end process;

end behavior;

2、结果图:

实验二实现例8.6

一、实验要求: 电路只有一个输入时钟信号,输出信号在适中的两个边沿都会发生变化

二、实验内容:

1、  代码

信号发生器vhd

ENTITY signal_gen IS

    PORT (clk: IN BIT;

             outp: OUT BIT);

END signal_gen;

ARCHITECTURE fsm OF signal_gen IS

    TYPE state IS (one, two, three);

    SIGNAL pr_state1, nx_state1: state;

    SIGNAL pr_state2, nx_state2: state;

    SIGNAL out1, out2: BIT;

BEGIN

PROCESS(clk)

BEGIN

   IF  (clk'EVENT AND clk = '1')  THEN

        pr_state1 <= nx_state1;

   END IF;

END PROCESS;

PROCESS (clk)

BEGIN

   IF (clk'EVENT AND clk = '0') THEN

       pr_state2 <= nx_state2;

   END IF;

END PROCESS;

PROCESS (pr_state1)

BEGIN

   CASE pr_state1 IS

      WHEN one =>

           out1 <= '0';

           nx_state1 <= two;

      WHEN two =>

           out1 <= '1';

           nx_state1 <= three;

      WHEN three =>

           out1 <= '1';

           nx_state1 <= one;

     END CASE;

END PROCESS;

PROCESS (pr_state2)

BEGIN

    CASE pr_state2 IS

        WHEN one =>

             out2 <= '1';

             nx_state2 <= two;

        WHEN two =>

             out2 <= '0';

             nx_state2 <= three;

        WHEN three =>

             out2 <= '1';

             nx_state2 <= one;

    END CASE;

END PROCESS;

outp <= out1 AND out2;

END fsm;

信号发生器tb

entity tb_fsm is

end tb_fsm;

architecture behavior of tb_fsm is

component signal_gen is

port( clk: in bit;

         outp: out bit);

end component;

signal clk,outp:bit;

begin

u1: signal_gen port map(clk,outp);

process

begin

clk<='0';

wait for 20 ns;

loop

clk<=not clk;

wait for 10 ns;

end loop;

end process;

end behavior;

2、  结果图

实验三常数比较器

一、实验要求 常数比较器,用于比较的变量位宽应大于等于常数

二、实验内容

1、  代码

常数比较器vhd

LIBRARY ieee;

USE ieee.std_logic_1164.all;

entity compare is

port(b: in integer range 0 to 15;

        x1,x2,x3: out std_logic);

end compare;

architecture compare of compare is

constant a: integer:=10;

begin

x1<='1' when a>b else '0';

x2<='1' when a=b else '0';

x3<='1' when a<b else '0';

end compare;

常数比较器tb

LIBRARY ieee;

USE ieee.std_logic_1164.all;

entity tb_compare is

end tb_compare;

architecture behavior of tb_compare is

component compare

port(b: in integer range 0 to 15;

        x1,x2,x3: out std_logic);

end component;

signal b: integer;

signal x1,x2,x3: std_logic;

begin

u1: compare port map(b, x1,x2,x3);

process

begin

b<=5; wait for 10 ns;

b<=8; wait for 10 ns;

b<=10; wait for 10 ns;

b<=13; wait for 10 ns;

b<=10; wait for 10 ns;

b<=3; wait for 10 ns;

end process;

end behavior;

2、  结果图

实验四序列检测器

一、实验要求  序列检测’1001’ 弱检测到,输出‘1‘,否则输出’0‘

二、实验内容

1、  状态图

2、  代码

序列检测器vhd

library ieee;

use ieee.std_logic_1164.all;

entity string_detector is

port(datain,clk: in bit;

        q: out bit);

end string_detector;

architecture sd of string_detector is

type state is (zero, one, two, three, four);

signal pr_state, nx_state: state;

begin

process(clk)

begin

if(clk'event and clk='1') then

pr_state<=nx_state;

end if;

end process;

process(datain, pr_state)

begin

case pr_state is

when zero=>

q<='0';

if(datain='1') then nx_state<=one;

else nx_state<=zero;

end if;

when one=>

q<='0';

if(datain='0') then nx_state<=two;

else nx_state<=zero;

end if;

when two=>

q<='0';

if(datain='0') then nx_state<=three;

else nx_state<=zero;

end if;

when three=>

q<='0';

if(datain='1') then nx_state<=four;

else nx_state<=zero;

end if;

when four=>

q<='1';

nx_state<=zero;

end case;

end process;

end sd;

序列检测器tb

------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

------------------------------------------------------------------

entity testBench is

end testBench;

------------------------------------------------------------------

architecture test of testBench is

    component string_detector is

    port(datain,clk: in bit;

        q: out bit);

    end component;

   

    signal datain,clk:bit;

    signal q:bit;

begin

    SD: string_detector port map(datain,clk,q);

    process

    begin

        for i in 0 to 100 loop

        clk<='0';

        wait for 10 ns;

        clk<='1';

        wait for 10 ns;

        end loop;

    end process;

   

    process

    begin

        din<='1';

        wait for 20ns;

        din<='0';

        wait for 20ns;

        din<='0';

        wait for 20ns;

        din<='0';

        wait for 20ns;

        din<='1';

        wait for 20ns;

        din<='0';

        wait for 20ns;

        din<='0';

        wait for 20ns;

        din<='1';

        wait for 20ns;

        din<='0';

        wait for 20ns;

        din<='1';

        wait for 20ns;

        din<='0';

        wait for 20ns;

    end process;

end test;

3、  结果图

      

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