EDA技术实验报告

实验报告

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EDA技术实验报告

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EDA技术实验报告

EDA技术实验报告

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第二篇：EDA技术与VHDL语言实验四加法器设计

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY add IS

PORT(

CIN : IN STD_LOGIC;

A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); AD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); BD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC);

END add;

ARCHITECTURE BEHAV OF add IS

SIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL AA,BB:STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN

AD<=A;BD<=B;

AA<='0' & A;

BB<='0' & B;

SINT<=AA+BB+CIN;

S<=SINT(3 DOWNTO 0);

COUT<=SINT(4);

END BEHAV;